| More Speed: DSM Moving Forward |
| Written by Dave Burstein |
 Infineon had the hit of the show, with a live demonstration of DSM Level 3 dramatically increasing speeds across six lines. They connected 6 lines through a spool of copper to a readout, all controlled by an FPGA. (The FPGA is under the fan in the top picture.) Without DSM, the interference brought down speeds, as you can see in the lower picture. They turned on DSM, and within seconds the speeds on the display went up dramatically. Christian Wolff tells me they are confident they can go quickly from FPGA to working chips and that their current 65 nanometer process is sufficient. ECI also had a working demo in their booth, and Broadcom had something off the floor.Reduce noise and dramatically increased throughput is possible, Cioffi convinced us all five years ago. Some of the noise reduction was relatively easy to achieve, techniques based on reducing power now called DSM Level 1. With very little publicity, that's been implemented on over 20M lines by Cioffi's company, ASSIA, and is now standard at half a dozen worldclass telcos. They've made major progress in reliability and preventing problem lines, but it will require a new generation of chips to reach the new, higher speeds of Level 3. In 2004, Cioffi predicted that by 2010 chips would be powerful enough to track the signals on all 25 or 50 pair in the binder group and cancel out noise. Reduce the noise and you can carry more information. DSM for now cancels only some kinds of noise. Impulse noise - an elevator turning on near the circuit, for example - is not managed. That may be an explanation of the positive but somewhat disappointing results in one test lab. World class engineers tell me the theory is sound, but look closely at any demonstrations that claim all the problems along the way have been solved. Conflict of interest reminder: ASSIA is a financial supporter, as you can see from their ads in DSL Prime.  |
